<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<project source="2.7.1" version="1.0">
  This file is intended to be loaded by Logisim (http://www.cburch.com/logisim/).

  <lib desc="#Wiring" name="0"/>
  <lib desc="#Gates" name="1"/>
  <lib desc="#Plexers" name="2"/>
  <lib desc="#Arithmetic" name="3"/>
  <lib desc="#Memory" name="4"/>
  <lib desc="#I/O" name="5"/>
  <lib desc="#Base" name="6">
    <tool name="Text Tool">
      <a name="text" val=""/>
      <a name="font" val="SansSerif plain 12"/>
      <a name="halign" val="center"/>
      <a name="valign" val="base"/>
    </tool>
  </lib>
  <main name="main"/>
  <options>
    <a name="gateUndefined" val="ignore"/>
    <a name="simlimit" val="1000"/>
    <a name="simrand" val="0"/>
  </options>
  <mappings>
    <tool lib="6" map="Button2" name="Menu Tool"/>
    <tool lib="6" map="Button3" name="Menu Tool"/>
    <tool lib="6" map="Ctrl Button1" name="Menu Tool"/>
  </mappings>
  <toolbar>
    <tool lib="6" name="Poke Tool"/>
    <tool lib="6" name="Edit Tool"/>
    <tool lib="6" name="Text Tool">
      <a name="text" val=""/>
      <a name="font" val="SansSerif plain 12"/>
      <a name="halign" val="center"/>
      <a name="valign" val="base"/>
    </tool>
    <sep/>
    <tool lib="0" name="Pin">
      <a name="tristate" val="false"/>
    </tool>
    <tool lib="0" name="Pin">
      <a name="facing" val="west"/>
      <a name="output" val="true"/>
      <a name="labelloc" val="east"/>
    </tool>
    <tool lib="1" name="NOT Gate"/>
    <tool lib="1" name="AND Gate"/>
    <tool lib="1" name="OR Gate"/>
  </toolbar>
  <circuit name="main">
    <a name="circuit" val="main"/>
    <a name="clabel" val=""/>
    <a name="clabelup" val="east"/>
    <a name="clabelfont" val="SansSerif plain 12"/>
    <wire from="(800,500)" to="(850,500)"/>
    <wire from="(730,590)" to="(780,590)"/>
    <wire from="(790,260)" to="(850,260)"/>
    <wire from="(400,260)" to="(450,260)"/>
    <wire from="(450,260)" to="(450,590)"/>
    <wire from="(490,530)" to="(490,540)"/>
    <wire from="(610,580)" to="(670,580)"/>
    <wire from="(530,500)" to="(780,500)"/>
    <wire from="(580,210)" to="(620,210)"/>
    <wire from="(730,260)" to="(770,260)"/>
    <wire from="(850,80)" to="(850,170)"/>
    <wire from="(850,500)" to="(850,590)"/>
    <wire from="(450,590)" to="(550,590)"/>
    <wire from="(490,540)" to="(530,540)"/>
    <wire from="(510,660)" to="(790,660)"/>
    <wire from="(790,450)" to="(790,490)"/>
    <wire from="(530,540)" to="(550,540)"/>
    <wire from="(530,280)" to="(550,280)"/>
    <wire from="(800,120)" to="(800,160)"/>
    <wire from="(580,230)" to="(600,230)"/>
    <wire from="(590,560)" to="(610,560)"/>
    <wire from="(490,210)" to="(520,210)"/>
    <wire from="(520,210)" to="(540,210)"/>
    <wire from="(580,270)" to="(670,270)"/>
    <wire from="(600,250)" to="(670,250)"/>
    <wire from="(510,330)" to="(780,330)"/>
    <wire from="(850,260)" to="(850,500)"/>
    <wire from="(530,230)" to="(540,230)"/>
    <wire from="(540,560)" to="(550,560)"/>
    <wire from="(800,590)" to="(850,590)"/>
    <wire from="(810,170)" to="(850,170)"/>
    <wire from="(850,170)" to="(850,260)"/>
    <wire from="(510,120)" to="(800,120)"/>
    <wire from="(450,260)" to="(550,260)"/>
    <wire from="(600,230)" to="(600,250)"/>
    <wire from="(610,560)" to="(610,580)"/>
    <wire from="(510,450)" to="(790,450)"/>
    <wire from="(530,500)" to="(530,540)"/>
    <wire from="(850,590)" to="(850,690)"/>
    <wire from="(590,540)" to="(620,540)"/>
    <wire from="(520,170)" to="(520,210)"/>
    <wire from="(580,600)" to="(670,600)"/>
    <wire from="(790,600)" to="(790,660)"/>
    <wire from="(780,270)" to="(780,330)"/>
    <wire from="(520,170)" to="(790,170)"/>
    <wire from="(540,610)" to="(550,610)"/>
    <comp lib="4" loc="(580,270)" name="Random">
      <a name="width" val="1"/>
    </comp>
    <comp lib="4" loc="(580,600)" name="Random">
      <a name="width" val="1"/>
    </comp>
    <comp lib="0" loc="(510,660)" name="Pin">
      <a name="tristate" val="false"/>
    </comp>
    <comp lib="0" loc="(620,210)" name="Pin">
      <a name="facing" val="west"/>
      <a name="output" val="true"/>
      <a name="labelloc" val="east"/>
    </comp>
    <comp lib="1" loc="(730,590)" name="XOR Gate"/>
    <comp lib="0" loc="(620,540)" name="Pin">
      <a name="facing" val="west"/>
      <a name="output" val="true"/>
      <a name="labelloc" val="east"/>
    </comp>
    <comp lib="0" loc="(530,230)" name="Constant"/>
    <comp lib="1" loc="(790,170)" name="Controlled Buffer">
      <a name="facing" val="west"/>
    </comp>
    <comp lib="0" loc="(510,330)" name="Pin">
      <a name="tristate" val="false"/>
    </comp>
    <comp lib="0" loc="(490,530)" name="Pull Resistor"/>
    <comp lib="0" loc="(400,260)" name="Clock"/>
    <comp lib="1" loc="(730,260)" name="XOR Gate"/>
    <comp lib="0" loc="(540,610)" name="Constant"/>
    <comp lib="0" loc="(530,280)" name="Constant"/>
    <comp lib="4" loc="(580,210)" name="T Flip-Flop"/>
    <comp lib="0" loc="(540,560)" name="Constant"/>
    <comp lib="1" loc="(780,500)" name="Controlled Buffer">
      <a name="facing" val="west"/>
    </comp>
    <comp lib="4" loc="(590,540)" name="T Flip-Flop"/>
    <comp lib="1" loc="(790,260)" name="Controlled Buffer"/>
    <comp lib="0" loc="(510,120)" name="Pin">
      <a name="tristate" val="false"/>
    </comp>
    <comp lib="0" loc="(490,210)" name="Pull Resistor"/>
    <comp lib="0" loc="(510,450)" name="Pin">
      <a name="tristate" val="false"/>
    </comp>
    <comp lib="1" loc="(800,590)" name="Controlled Buffer"/>
    <comp lib="6" loc="(4,16)" name="Text">
      <a name="text" val="Designed by S. Gražulis (https://saulius.grazulis.lt) CC-BY-NC"/>
      <a name="halign" val="left"/>
    </comp>
  </circuit>
</project>
