module rng (
            input  clk,
            output LED1,
            output LED2,
            output LED3,
            output LED4,
            output LED5
            );

   localparam BITS = 5;
   //localparam LOG2DELAY = 22;
   localparam LOG2DELAY = 22;

   //reg [4:0]                leds = 5'b00011;
   reg [BITS+LOG2DELAY-1:0] counter = 0;
   reg                      ready = 0;   
   reg [31:0]               rng;

   always@(posedge clk)
     counter <= counter + 1;

   always@(posedge counter[LOG2DELAY-2])
     if( ready )
       begin
          //leds[1] <= leds[2];
          //leds[2] <= leds[3];
          //leds[3] <= leds[4];
          //leds[4] <= leds[1];
          rng <= ({rng[0],(rng >> 1)})^(rng | {(rng << 1),rng[31]});
       end
     else
       begin
          //leds = 5'b00011;
          rng = 32'h00010000;
          ready = 1;
       end

   assign {LED1, LED2, LED3, LED4, LED5} = rng[11:7];
   //assign {LED1, LED2, LED3, LED4, LED5} = leds[4:0];

endmodule