`include "rng.v"

module simulate();
   reg clk;
   wire LED1, LED2, LED3, LED4, LED5;

   rng rng1(clk, LED1, LED2, LED3, LED4, LED5);

   always #1 clk = !clk;
   
   initial
     begin
        $display( "Begin Simulation" );
        clk = 0;
        $monitor("At time %t, LEDS = %h %h %h %h %h",
                 $time, LED1, LED2, LED3, LED4, LED5 );
        #100000000 $finish;
        $display( "End Simulation" );
     end
   
endmodule