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%$Date: 2020-06-04 14:58:32 +0300 (Thu, 04 Jun 2020) $ 
%$Revision: 1524 $
%$URL: svn+ssh://saulius-grazulis.lt/home/saulius/svn-repositories/seminarai/2020-verifikacjos-seminarui/slides.tex $
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%%BEGIN LANGUAGE en
\title{RISC architectures}
%%END LANGUAGE en


\author{Saulius Gražulis}

\date{Vilnius, \the\year}

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    %%   $Id: slides.tex 1524 2020-06-04 11:58:32Z saulius $
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        %%BEGIN LANGUAGE en
        This set of slides may be copied and used as specified in the
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license
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%==============================================================================

%% \begin{frame}[allowframebreaks]
%%   %%LANGUAGE en \frametitle{RISC-V}
%%   %%LANGUAGE lt \frametitle{RISC-V}
%%   %%LANGUAGE ru \frametitle{RISC-V}
%% 
%%   \begin{enumerate}
%%   \item RISC vs CISC
%%   \item Uniform instruction size, etc.
%%   \item RISC-V – an open architecture
%%   \item RV sets
%%   \item Registers
%%   \item Special registers
%%   \item Instruction formats
%%   \item Addressing modes
%%   \item Immediate operands; 12-20 split
%%   \item LUI
%%   \item Carry/overflow detection
%%   \item Atomic memory access
%%   \item Multiplications: high/low bytes
%%   \item Short branches, long jumps
%%   \item Subroutine calls; link register
%%   \item Multiprecision arithmetic; SLT
%%   \item Floating point
%%   \item Syscall/Break
%%   \item !!! Pipelines
%%   \item Code density; compressed instr. sets
%%   \item Alignment
%%   \item Vector extensions
%%   \item Notable RISC-V examples
%%   \item Notable RISC examples
%%   \end{enumerate}
%%   
%% \end{frame}

%------------------------------------------------------------------------------

\begin{frame}
\frametitle{x86}

  \only<1>{
    \textcolor{blue}{
Advantages:
    }
    \begin{itemize}
    \item
Compatibility over 40 years
    \item
      %%BEGIN LANGUAGE en
      Fastest possible simultaneous execution of all code, both old
      an new
      %%END LANGUAGE en
    \item
Fastest systems
    \end{itemize}
  }
  \only<2>{
    \textcolor{red}{
Drawbacks:
    }
    \begin{itemize}
    \item
Large, complicated chips
    \item
Large transistor count – large power dissipation
    \item
Some obsolete features present just for compatibility
    \item
Some functions are duplicated
    \item
A lot of features not used in any given application – ballast
    \item
      %%BEGIN LANGUAGE en
      A lot of specialised with special behaviour instructions –
      difficulties for compiler writers
      %%END LANGUAGE en
    \end{itemize}

    \vspace{\baselineskip}
    ``AMD’s 80x86 architect, Mike Johnson, famously quipped, “The x86
    really isn’t all that complex—it just doesn’t make a lot of sense”
    \rightline{\mycite{Waterman2016c}}
  } \transdissolve<2>
  
\end{frame}

%------------------------------------------------------------------------------

\begin{frame}
\frametitle{The case for RISC}

  \only<1>{
    \begin{itemize}
    \item
      ``Semiconductor memories are both fast and relatively
      inexpensive'' \mycite{Patterson2003}
    \item
      ``it is difficult to have "rational" implementations'' (ibid.)
      \begin{itemize}
      \item
        IBM 370: Peuto and Shustek have discovered that a sequence of
        load instructions is faster than a load multiple instruction for
        fewer than 4 registers; this covers 40\% of cases in typical
        programs \mycite{Patterson2003,Peuto1977}
      \item
        Patterson found that for VAX~11/780 replacing complex INDEX
        instruction (calculates address of an array element, checks
        bounds) by several simple instructions (COMPARE, JUMP LESS
        UNSIGNED, ADD, MUL) can calculate the same function
        \textbf{45\%} faster (in special cases, \textbf{60\%} faster!)
        \mycite{Patterson2003}
      \end{itemize}
    \end{itemize}
  }
  \only<2>{
    \begin{itemize}
    \item
      ``measurements of a particular IBM 360 compiler found that 10
      instructions accounted for 80\% of all instructions executed, 16
      for 90\%, 21 for 95\%, and 30 for 99\%''\footnote{ IBM 360 had 8
        bit opcodes, so would have no more than 256 different
        instructions – with various operands
        (``\myhref{http://bitsavers.org/pdf/ibm/360/princOps/A22-6821-0\_360PrincOps.pdf}{IBM
          System/360 Principles of Operation}'', p.~14) }
      \mycite{Patterson2003,Alexander1975}.
    \item
      ``pushing a register on the stack with \textbf{PUSHL R0} is
      slower than pushing it with the move instruction \textbf{MOVL
        R0,-(SP)} on the VAX 11/78'' \mycite{Patterson2003}
    \end{itemize}
  }

\end{frame}

%------------------------------------------------------------------------------

\begin{frame}
\frametitle{RISC}

  \only<1>{
Technical features:
  }
  \only<2>{
Design decisions:
  }
  
  \begin{center}
    \footnotesize
    \renewcommand{\arraystretch}{1.5}
    \only<1>{
      \begin{tabular}{lp{0.3\textwidth}p{0.3\textwidth}}
        \hline
        & RISC & CISC \\
        \hline
        Instructions
        &
        \raggedright
        Simple: Load/Store regs, operations \textbf{only} in regs
        &
        Complex tasks for multiple data types, both in regs and in memory
        \\
        Instr. formats
        &
        \parbox[t]{\linewidth}{
          \raggedright
          Fixed length, two main types: load/store \& \mbox{\texttt{R :=
              R op R}}
        }
        &
        \parbox[t]{\linewidth}{
          \raggedright
          Variable length, may types: load/store, \mbox{\texttt{R := R op R}},
          \mbox{\texttt{R := R op Mem}}, \mbox{\texttt{R := Mem op Mem}}
        }
        \\
        Registers
        &
        16–32 general purpose
        &
        \parbox[t]{\linewidth}{
          \raggedright
          Specialised or 8–16 general purpose

          \vspace{0.5\baselineskip}
        }
        \\
        \hline
      \end{tabular}
    }
    \only<2>{
      \begin{tabular}{lp{0.3\textwidth}p{0.3\textwidth}}
        \hline
        & RISC & CISC \\
        \hline
        Design objective
        &
        \parbox[t]{\linewidth}{
          \raggedright
          Trade off program length, minimise time to execute instruction
        }
        &
        \parbox[t]{\linewidth}{
          \raggedright
          Minimise program length, maximise work/instruction
        }
        \\
        Implementation
        &
        Hard-wired
        &
        Microprogrammed
        \\
        Caching
        &
        Essential (at least for code)
        &
        \parbox[t]{\linewidth}{
          \raggedright
          Useful ($\Rightarrow$ nowadays, essential)
        }
        \\
        Compiler design
        &
        \parbox[t]{\linewidth}{
          \raggedright
          Find best instruction ordering \& register allocation
        }
        &
        \parbox[t]{\linewidth}{
          \raggedright
          Find best/right instructions
        }
        \\
        Philosophy
        &
        \parbox[t]{\linewidth}{
          \raggedright
          Move all (complicated) functions to software
        }
        &
        \parbox[t]{\linewidth}{
          \raggedright
          Move any useful software function into hardware

          \vspace{0.5\baselineskip}
        }
        \\
        \hline
      \end{tabular}
    }
  \end{center}
  \rightline{\scriptsize Adapted from: \mycite{Jamil1995}}
  \transdissolve<2>
  
\end{frame}

%------------------------------------------------------------------------------

\begin{frame}
\frametitle{Some RISC machines}

  \only<1>{
Past...
    
    \begin{center}
      \begin{minipage}{0.45\textwidth}
        \begin{center}
          \includegraphics[height=4.5cm]{images/SGI/800px-SGI_Indigo2_High_Impact_workstation_next_to_an_SGI_Espressigo.jpg}
        \end{center}
      \end{minipage}
      \hspace{1ex}
      \begin{minipage}{0.45\textwidth}
        \begin{center}
          \includegraphics[height=4.5cm]{images/Sun/SPARCstation_1.jpg}
        \end{center}
      \end{minipage}
    \end{center}
  }

  \only<2>{
And possibly future...

    \begin{center}
      \begin{minipage}{0.3\textwidth}
        \begin{center}
          \includegraphics[height=4.5cm]{images/Apple/644px-Apple_M1_from_Gimp.jpg}
          %% Henriok, CC0, via Wikimedia Commons
        \end{center}
      \end{minipage}
      %
      \begin{minipage}{0.49\textwidth}
        \includegraphics[height=4.5cm]{images/RISC-V/800px-Yunsup_Lee_holding_RISC_V_prototype_chip.jpg}
      \end{minipage}
    \end{center}
  }
\end{frame}

%------------------------------------------------------------------------------

\begin{frame}
\frametitle{RISC-V}

  \includegraphics[width=\textwidth]{images/RISC-V/RISC-V-logo.eps}

  \begin{itemize}
  \item
Open-standard RISC ISA :)
  \item
Is provided under open source licenses
  \item
Does not require royalty fees to use
  \item
    %%BEGIN LANGUAGE en
    A number of companies are offering or have announced RISC-V
    hardware
    %%END LANGUAGE en
  \item
    %%BEGIN LANGUAGE en
    open source operating systems and tool-chains (compilers,
    assemblers) with RISC-V support are available
    %%END LANGUAGE en
  \end{itemize}
  
\end{frame}

%------------------------------------------------------------------------------

\begin{frame}
\frametitle{RISC-V variants}

  \begin{itemize}
  \item
3 address widths:
    \begin{itemize}
      \item RV32
      \item RV64
      \item RV128
    \end{itemize}
    \only<1>{
    \item
Multiple extensions:
      \begin{itemize}
      \item I – base integer ISA
      \item M – hardware multiply and divide
      \item A – atomic synchronisation support
      \item F – single precision floating point
      \item D – double precision floating point
      \end{itemize}
    }
    \only<2>{
    \item
More exotic extensions
      \begin{itemize}
        \item S – Supervisor mode is implemented
        \item Q – Quad-precision (128 bit) floating point is supported
        \item C – Compressed (i.e., 16 bit) instructions are supported
        \item E – Embedded microprocessors, with only 16 registers
      \end{itemize}
    }
    \only<3>{
    \item
Future extensions:
      \begin{itemize}
        \item L – Decimal arithmetic instructions
        \item V – Vector arithmetic instructions
        \item P – Packed SIMD instructions
        \item B – Bit manipulation instructions
        \item T – Transactional memory support
      \end{itemize}
    }
  \end{itemize}
  \transdissolve<2-3>

  \centerline{RV32G = RV32IMAFD}
  
\end{frame}

%------------------------------------------------------------------------------

\begin{frame}
\frametitle{Main memory}

  \begin{itemize}
  \item
32-bit, 64-bit or 128-bit (virtual) address widths
  \item
Little-endian
  \item
Supports unaligned access
  \item
Virtual memory: paging
  \item
I/O: memory mapped
  \end{itemize}
  
\end{frame}

%------------------------------------------------------------------------------

\begin{frame}
\frametitle{RISC-V registers}

  \begin{itemize}
  \item
32 general purpose registers
  \item
    %%BEGIN LANGUAGE en
    if floating point is supported, there will be additional 32
    floating point registers
    %%END LANGUAGE en
  \item
    ``it would be possible to define a non-standard subset integer
    RISC-V ISA with 16 registers'' \mycite{Waterman2014}
  \item
Register widths either 32, 64 or 128 bits
  \end{itemize}
  
\end{frame}

%------------------------------------------------------------------------------

\begin{frame}
\frametitle{RISC-V register set}

  \begin{center}
    \includegraphics[width=10cm,page=30,trim=3cm 14.5cm 3cm 4cm,clip]{bibliography/PDF/2016_Waterman_1c.pdf}
  \end{center}

  RV32I
Programmer-visible register set
  \mycite{Waterman2016c}
  
\end{frame}

%------------------------------------------------------------------------------

\begin{frame}
\frametitle{Instructions}

  \begin{itemize}
  \item
all basic instructions are 32 bit wide
  \item
must be stored at word-aligned memory locations
  \item
... but 16 bit compressed extensions relax alignment to 16 bits
  \item
    %%BEGIN LANGUAGE en
    Instructions for the RV64 and RV128 variants are also 32 bits
    long
    %%END LANGUAGE en
  \item
    RISC-V
is a “three address” architecture. E.g.:

    \centerline{\tt add x4,x5,x7 \# x4 = x5 + x7}
  \item
    16-bit instructions are optionally supported to compress code (the
    ``C'' extension), but they are \textit{synonyms} of the standard
    32-bit instructions
  \end{itemize}

  \rightline{\mycite{Porter2018}}
  
\end{frame}

%------------------------------------------------------------------------------

\begin{frame}
\frametitle{Instruction formats}

  \begin{center}
    \includegraphics[width=12cm,page=21,trim=3cm 18.5cm 3cm 5.5cm,clip]{bibliography/PDF/2014_Waterman_1.pdf}
  \end{center}

  \rightline{\mycite{Waterman2014}}

\end{frame}

%------------------------------------------------------------------------------

\begin{frame}
\frametitle{Instruction types}

  \begin{itemize}
  \item<1->
R-type instructions:
    \centerline{\tt add x3,x5,x6 \# x3 = x5 + x6}
  \item<2->
I-type instructions:
    \centerline{\tt addi x4,x6,123 \# x4 = x6+123}
    \centerline{\tt lw x4,8(x6) \# x4 = Mem[8+x6]}
  \item<3->
S-type instructions:
    \centerline{\tt sw x4,8(x6) \# Mem[8+r6] = x4 (word)}
  \item<4->
B-type instructions (a variant of S-type):
    \centerline{\tt blt x4,x6,loop \# if x4<x6, goto offset + pc}
  \item<5->
U-type instructions:
    \centerline{\tt lui x4,0x12AB7 \# x4 = value<<12}
    \centerline{\tt auipc x4,0x12AB7 \# x4 = (value<<12) + pc}
  \item<6->
J-type instructions (a variant of U-type):
    \centerline{\tt jal \# call: pc = offset + pc; x4 = ret add}
  \end{itemize}
  
\end{frame}

%------------------------------------------------------------------------------

\begin{frame}
\frametitle{Addressing modes}

Just 2 addressing modes!

  \begin{itemize}
  \item
immediate (operand in the instruction)
  \item
register indirect + offset
  \end{itemize}

Immediate values:

  \begin{center}
    \tt
    \parbox{0.5\textwidth}{
      \leftline{addi x5,x0,21}

      \vspace{\baselineskip}
      \leftline{lui x6,x0,0x1234}
      \leftline{addi x6,x0,0x5678 \# x6 = 0x12345678}
    }
  \end{center}
    
\end{frame}

%------------------------------------------------------------------------------

\begin{frame}
\frametitle{Memory access instructions}

  \begin{center}
    \includegraphics[width=11cm,page=35,trim=4cm 18.3cm 4cm 4cm,clip]{bibliography/PDF/2016_Waterman_1c.pdf}
  \end{center}

  \rightline{\mycite{Waterman2016c}}
\end{frame}

%------------------------------------------------------------------------------

\begin{frame}
\frametitle{Register x0}

  %%BEGIN LANGUAGE en
  Register \texttt{x0} always contains $0$ (and writes to it are
  ignored).
  %%END LANGUAGE en

Interregister \texttt{MOV} instruction not necessary!

  \begin{center}
    \texttt{add x6,x7,x0}
  \end{center}

is used instead of
  
  \begin{center}
    \texttt{mov x6,x7}
  \end{center}

\end{frame}

%------------------------------------------------------------------------------

\begin{frame}
\frametitle{Register x1}

  %%BEGIN LANGUAGE en
  Register \texttt{x1} is used to store return address during
  subroutine calls, \textbf{by convention} (any other register could
  do!).
  %%END LANGUAGE en

  \vspace{\baselineskip}
The return is then just \texttt{jr x1} (Jump using Register)

  \vspace{\baselineskip}
For recursive calls x1 needs to be saved!
  
\end{frame}

%------------------------------------------------------------------------------

\begin{frame}
\frametitle{MUL implementation}

  \visible<1->{
    %%BEGIN LANGUAGE en
    Lower part bits of multiplication are the same for signed and
    unsigned multiplication $\Rightarrow$ only one \texttt{MUL}
    instruction is needed:
    %%END LANGUAGE en

    \begin{center}
      \tt mul x4,x9,x13 \# x4 = x9*x13
    \end{center}
  }

  \visible<2->{
    %%BEGIN LANGUAGE en
    However the higher portion can be different for signed and unsigned
    operands, thus 3 instructions produce high bits:
    %%END LANGUAGE en

    \begin{center}
      \tt
      \leftline{
        MULH –
signed operands
      }
      \leftline{
        MULHU –
unsigned operands
      }
      \leftline{
        MULHSU –
one signed operand and one unsigned operand
      }
    \end{center}
  }
  
  \vspace{-\baselineskip}
  \visible<3>{
    %%BEGIN LANGUAGE en
    Operations should be performed in this order and can then be
    (optionally) fused by hardware:
    %%END LANGUAGE en

    \begin{center}
      \begin{minipage}{0.75\textwidth}
        \tt
        \leftline{mulh x4,x9,x13 \# compute upper half}
        \leftline{mul\ \ x5,x9,x13 \# compute lower half}
        \leftline{\# The product is now in the register pair x4:x5}
      \end{minipage}
    \end{center}
  }

\end{frame}

%------------------------------------------------------------------------------

\begin{frame}
\frametitle{JMP implementation}

  %%BEGIN LANGUAGE en
  Instruction for \texttt{JMP} is \textit{always} jump-and-link:
  \texttt{jal} or \texttt{jalr}.

  \vspace{\baselineskip}
  But, if you do not need the return address, use \texttt{x0} as a
  link register :)
  %%END LANGUAGE en

  \centerline{\tt jal x0, loop}
  
\end{frame}

%------------------------------------------------------------------------------

\begin{frame}
\frametitle{Stack. x2}

  \begin{itemize}
  \item
    %%BEGIN LANGUAGE en
    A function that requires stack storage will grow the stack (always
    by a multiple of 16) by subtracting from the stack top pointer sp.
    %%END LANGUAGE en
  \item
    %%BEGIN LANGUAGE en
    Variables within the stack frame can be addressed using positive
    offsets from register x2.
    %%END LANGUAGE en
  \end{itemize}
  
\end{frame}

%------------------------------------------------------------------------------

\begin{frame}
\frametitle{GP: x3}

  \begin{itemize}
  \item
    %%BEGIN LANGUAGE en
    The RISC-V calling convention is to place the global variables
    together and initialise a register to point to this area.
    %%END LANGUAGE en

  \item
By convention, register x3 is used for this.

  \item
    %%BEGIN LANGUAGE en
    The individual variables can be conveniently
    addressed by using a small offset from the global pointer.
    %%END LANGUAGE en

  \item
    %%BEGIN LANGUAGE en
    The global pointer is typically initialised early in the program
    and never changed. So, in some sense, it is “callee-saved”
    %%END LANGUAGE en
  \end{itemize}
  
\end{frame}

%------------------------------------------------------------------------------

\begin{frame}
\frametitle{Other registers}

  \begin{itemize}
  \item
Register \texttt{x4} -- The Thread Base Pointer (“tp”)
  \item
    %%BEGIN LANGUAGE en
    Register x8,x9,x18-x27 -- Saved Registers (“s0-s11”)
    (\textit{Callee saved})
    %%END LANGUAGE en
  \item
    %%BEGIN LANGUAGE en
    Register x5-x7,x28-x31 -- Temporary Registers (“t0-t6”)
    (\textit{Caller saved})
    %%END LANGUAGE en
  \item
Register x10-x17 - Argument Registers (“a0-a7”)
    \footnote{
      %%BEGIN LANGUAGE en
      Floating point arguments are passed in the floating point,
      \texttt{fn} registers if they exist.
      %%END LANGUAGE en
    }
    
  \end{itemize}
  
\end{frame}

%------------------------------------------------------------------------------

\lstset{
  basicstyle=\tt\scriptsize,
  keywordstyle=\color{KwdColor},
  commentstyle=\color{CommentColor}\ttfamily,
  identifierstyle=\color{IdentifierColor},
  stringstyle=\color{StringColor},
  morecomment=[l]{\#},
  morekeywords={add,li,sltu,ecall,ebreak}
}

\begin{frame}
\frametitle{Example: multiple precision add}

  \only<1>{
    \lstinputlisting[language=bash,morekeywords={add,li,sltu,ecall,ebreak}]{examples/RISC-V/RARS/multiprecision-add-with-SLTU.asm}
  }
  \only<2>{
    \lstinputlisting[language=bash,morekeywords={add,li,sltu,ecall,ebreak}]{examples/RISC-V/RARS/multiprecision-add-with-BGEU.asm}
  }
  \transdissolve<2>

\end{frame}

%------------------------------------------------------------------------------

\begin{frame}%%[allowframebreaks]
\frametitle{References}

  \setmainfont{Liberation Serif}
  \renewcommand{\bibfont}{\scriptsize}
  \printbibliography

\end{frame}

%------------------------------------------------------------------------------                                                                                                          
\end{document}
% 2020-12-14 20:14:58 EET
