Index of /~saulius/paskaitos/VU/kompiuterių-architektūra/skaidrės

[ICO]NameLast modifiedSizeDescription
[PARENTDIR]Parent Directory  -  
[ ]01_intro.mltex2023-09-11 15:16 44K 
[ ]01_intro_en.pdf2023-09-11 15:16 9.5M 
[TXT]01_intro_en.tex2023-09-11 15:16 22K 
[ ]01_intro_lt.pdf2023-09-11 15:16 9.7M 
[TXT]01_intro_lt.tex2023-09-11 15:16 23K 
[ ]02_logic-gates.mltex2023-09-11 15:16 64K 
[ ]02_logic-gates_en.pdf2023-09-11 15:16 2.2M 
[TXT]02_logic-gates_en.tex2023-09-11 15:16 46K 
[ ]02_logic-gates_lt.pdf2023-09-11 15:16 2.2M 
[TXT]02_logic-gates_lt.tex2023-09-11 15:16 46K 
[ ]03_binary-arithmetic.mltex2023-09-11 05:53 74K 
[ ]03_binary-arithmetic_en.pdf2023-09-11 05:53 627K 
[TXT]03_binary-arithmetic_en.tex2023-09-11 05:53 51K 
[ ]03_binary-arithmetic_lt.pdf2023-09-11 05:53 630K 
[TXT]03_binary-arithmetic_lt.tex2023-09-11 05:53 51K 
[ ]04_neg-numbers-clocks-triggers.mltex2020-10-11 13:19 35K 
[ ]04_neg-numbers-clocks-triggers_en.pdf2020-12-20 20:59 533K 
[TXT]04_neg-numbers-clocks-triggers_en.tex2020-10-11 13:19 25K 
[ ]04_neg-numbers-clocks-triggers_lt.pdf2020-10-11 13:19 534K 
[TXT]04_neg-numbers-clocks-triggers_lt.tex2020-10-11 13:19 25K 
[ ]05_decoders-busses-memory.mltex2020-10-11 17:24 19K 
[ ]05_decoders-busses-memory_en.pdf2020-12-20 20:59 7.5M 
[TXT]05_decoders-busses-memory_en.tex2020-10-11 17:24 15K 
[ ]05_decoders-busses-memory_lt.pdf2020-10-11 17:24 7.5M 
[TXT]05_decoders-busses-memory_lt.tex2020-10-11 17:24 15K 
[ ]06_CPU_implementation.mltex2020-10-11 13:34 8.7K 
[ ]06_CPU_implementation_en.pdf2020-12-20 20:59 563K 
[TXT]06_CPU_implementation_en.tex2020-10-11 13:34 6.3K 
[ ]06_CPU_implementation_lt.pdf2020-10-11 13:34 564K 
[TXT]06_CPU_implementation_lt.tex2020-10-11 13:34 6.4K 
[ ]07_machine-code-and-assembler.mltex2021-10-18 07:02 36K 
[ ]07_machine-code-and-assembler_en.pdf2023-12-03 09:28 424K 
[TXT]07_machine-code-and-assembler_en.tex2021-10-18 07:02 19K 
[ ]07_machine-code-and-assembler_lt.pdf2023-12-03 09:28 425K 
[TXT]07_machine-code-and-assembler_lt.tex2021-10-18 07:02 19K 
[ ]08_kontrolinio_aptarimas.mltex2020-11-15 17:32 15K 
[ ]08_kontrolinio_aptarimas_en.pdf2020-12-20 20:59 299K 
[TXT]08_kontrolinio_aptarimas_en.tex2020-11-30 06:01 10K 
[ ]08_kontrolinio_aptarimas_lt.pdf2020-11-22 10:31 299K 
[TXT]08_kontrolinio_aptarimas_lt.tex2020-11-15 17:32 11K 
[ ]08_x86-architecture.mltex2023-11-13 09:32 24K 
[ ]08_x86-architecture_en.pdf2023-12-03 09:28 602K 
[TXT]08_x86-architecture_en.tex2023-11-13 09:32 15K 
[ ]08_x86-architecture_lt.pdf2023-12-03 09:28 602K 
[TXT]08_x86-architecture_lt.tex2023-11-13 09:32 15K 
[ ]09_x86-ISA.mltex2023-11-27 09:07 31K 
[ ]09_x86-ISA_en.pdf2023-12-03 09:28 844K 
[TXT]09_x86-ISA_en.tex2023-11-27 09:07 20K 
[ ]09_x86-ISA_lt.pdf2023-12-03 09:28 845K 
[TXT]09_x86-ISA_lt.tex2023-11-27 09:07 19K 
[ ]10_x86_paging_caching_floating_point.mltex2020-12-06 15:58 16K 
[ ]10_x86_paging_caching_floating_point_en.pdf2020-12-20 20:59 4.0M 
[TXT]10_x86_paging_caching_floating_point_en.tex2020-12-06 15:58 11K 
[ ]10_x86_paging_caching_floating_point_lt.pdf2020-12-06 15:58 4.0M 
[TXT]10_x86_paging_caching_floating_point_lt.tex2020-12-06 15:58 12K 
[ ]11_floating_point.mltex2021-11-29 08:18 42K 
[ ]11_floating_point_en.pdf2021-11-29 08:18 712K 
[TXT]11_floating_point_en.tex2021-11-29 08:18 24K 
[ ]11_floating_point_lt.pdf2021-11-29 08:18 713K 
[TXT]11_floating_point_lt.tex2021-11-29 08:18 24K 
[ ]12_RISC-V.mltex2020-12-14 18:15 41K 
[ ]12_RISC-V_en.pdf2020-12-20 20:59 841K 
[TXT]12_RISC-V_en.tex2020-12-14 18:15 23K 
[ ]12_RISC-V_lt.pdf2020-12-14 18:15 844K 
[TXT]12_RISC-V_lt.tex2020-12-14 18:15 23K 
[ ]13_pipelines.mltex2023-12-18 09:00 16K 
[ ]13_pipelines_en.pdf2023-12-18 09:00 648K 
[TXT]13_pipelines_en.tex2023-12-18 09:00 9.8K 
[ ]13_pipelines_lt.pdf2023-12-18 09:00 648K 
[TXT]13_pipelines_lt.tex2023-12-18 09:00 9.9K 
[ ]14_non-traditional-architectures.mltex2021-01-04 15:59 23K 
[ ]14_non-traditional-architectures_en.pdf2021-01-04 15:59 5.0M 
[TXT]14_non-traditional-architectures_en.tex2021-01-04 15:59 19K 
[ ]14_non-traditional-architectures_lt.pdf2021-01-04 15:59 5.0M 
[TXT]14_non-traditional-architectures_lt.tex2021-01-04 15:59 19K 
[DIR]bibliography/2021-11-15 06:45 -  
[DIR]drawings/2021-01-03 19:19 -  
[DIR]examples/2021-11-15 07:57 -  
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