Index of /~saulius/paskaitos/VU/kompiuterių-architektūra/skaidrės/drawings/circuits

[ICO]NameLast modifiedSizeDescription
[PARENTDIR]Parent Directory  -  
[ ]CMOS-AND-NOT-gates-A0-B0.xcf2020-09-02 07:27 31K 
[ ]CMOS-NOR-NOT-gates-A0-B0.xcf2021-09-12 21:09 27K 
[ ]CMOS-NOR-NOT-gates-A1-B0.xcf2021-09-13 14:50 27K 
[ ]CMOS-NOR-NOT-gates-A0-B1.xcf2021-09-13 14:50 27K 
[ ]CMOS-NOR-NOT-gates-A1-B1.xcf2021-09-13 14:50 27K 
[ ]CMOS-OR-gate-A0-B0.xcf2020-09-02 07:27 23K 
[ ]CMOS-AND-gate-A0-B1.xcf2020-09-02 07:27 22K 
[ ]CMOS-AND-gate-A0-B0.xcf2020-09-02 07:27 22K 
[ ]CMOS-AND-gate-A1-B1.xcf2020-09-02 07:27 22K 
[ ]CMOS-AND-gate-A1-B0.xcf2020-09-02 07:27 22K 
[ ]CMOS-OR-gate-A1-B0.xcf2020-09-02 07:27 22K 
[ ]CMOS-OR-gate-A1-B1.xcf2020-09-02 07:27 22K 
[ ]CMOS-OR-gate-A0-B1.xcf2020-09-02 07:27 22K 
[ ]CMOS-NAND-gate-A1-B0.xcf2020-09-02 07:27 22K 
[ ]CMOS-NAND-gate-A1-B1.xcf2020-09-02 07:27 21K 
[ ]CMOS-NAND-gate-A0-B1.xcf2020-09-02 07:27 21K 
[ ]CMOS-NAND-gate-A0-B0.xcf2020-09-02 07:27 21K 
[ ]CMOS-NOR-gate-A1-B0.xcf2021-09-12 20:29 19K 
[ ]CMOS-NOR-gate-A0-B0.xcf2021-09-12 20:29 19K 
[ ]CMOS-NOR-gate-A1-B1.xcf2021-09-12 20:29 19K 
[ ]CMOS-NOR-gate-A0-B1.xcf2021-09-12 20:29 19K 
[ ]CMOS-AND-gate-half-A0-B1.xcf2020-09-02 07:27 19K 
[ ]CMOS-AND-gate-half-A1-B0.xcf2020-09-02 07:27 19K 
[ ]CMOS-AND-gate-half-A0-B0.xcf2020-09-02 07:27 19K 
[ ]CMOS-AND-gate-half-A1-B1.xcf2020-09-02 07:27 18K 
[ ]CMOS-NOT-gate-input-Low.xcf2020-09-02 07:27 17K 
[ ]CMOS-NOT-gate-input-High.xcf2020-09-02 07:27 17K 
[ ]CMOS-NAND-gate-half-A1-B1.xcf2021-09-12 16:45 15K 
[ ]CMOS-NAND-gate-half-A0-B1.xcf2021-09-12 16:45 15K 
[ ]CMOS-NAND-gate-half-A0-B0.xcf2021-09-12 16:45 15K 
[ ]CMOS-NAND-gate-half-A1-B0.xcf2021-09-12 16:45 15K 
[ ]CMOS-NOR-NOT-gates.circ2021-09-12 21:09 5.2K 
[ ]CMOS-AND-NOT-gates.circ2020-09-02 07:27 5.2K 
[ ]CMOS-AND-gate.circ2020-09-02 07:27 4.1K 
[ ]CMOS-OR-gate.circ2020-09-02 07:27 4.0K 
[ ]CMOS-NOR-gate.circ2020-09-02 07:27 3.8K 
[ ]CMOS-NAND-gate.circ2020-09-02 07:27 3.8K 
[IMG]CMOS-NOR-NOT-gates-A0-B1.png2021-09-13 14:50 3.5K 
[IMG]CMOS-NOR-NOT-gates-A1-B1.png2021-09-13 14:50 3.5K 
[IMG]CMOS-NOR-NOT-gates-A1-B0.png2021-09-13 14:50 3.5K 
[IMG]CMOS-NOR-NOT-gates-A0-B0.png2021-09-12 21:09 3.5K 
[ ]CMOS-AND-gate-half.circ2020-09-02 07:27 3.4K 
[ ]CMOS-NAND-gate-half.circ2021-09-12 16:45 3.2K 
[ ]CMOS-NOT-gate.circ2020-09-02 07:27 3.1K 
[ ]CMOS-NOR-gate-half.circ2020-09-02 07:27 3.1K 
[IMG]CMOS-NOR-gate-A0-B1.png2021-09-12 20:29 2.6K 
[IMG]CMOS-NOR-gate-A1-B0.png2021-09-12 20:29 2.6K 
[IMG]CMOS-NOR-gate-A1-B1.png2021-09-12 20:29 2.6K 
[IMG]CMOS-NOR-gate-A0-B0.png2021-09-12 20:29 2.6K 
[IMG]CMOS-OR-gate-A0-B0.png2020-09-02 07:27 2.5K 
[IMG]CMOS-NAND-gate-A1-B0.png2020-09-02 07:27 2.3K 
[IMG]CMOS-NAND-gate-half-A1-B1.png2021-09-12 16:45 2.3K 
[IMG]CMOS-NAND-gate-half-A0-B1.png2021-09-12 16:45 2.3K 
[IMG]CMOS-NAND-gate-half-A0-B0.png2021-09-12 16:45 2.3K 
[IMG]CMOS-NAND-gate-half-A1-B0.png2021-09-12 16:45 2.3K 
[IMG]CMOS-AND-gate-half-A1-B0.png2020-09-02 07:27 2.2K 
[IMG]CMOS-NOT-gate-input-Low.png2020-09-02 07:27 2.1K 
[IMG]CMOS-AND-gate-half-A0-B0.png2020-09-02 07:27 1.9K 
[IMG]CMOS-AND-NOT-gates-A0-B0.png2020-09-02 07:27 1.8K 
[IMG]CMOS-NOT-gate-input-High.png2020-09-02 07:27 1.8K 
[IMG]CMOS-AND-gate-A0-B1.png2020-09-02 07:27 1.7K 
[IMG]CMOS-OR-gate-A1-B0.png2020-09-02 07:27 1.7K 
[IMG]CMOS-OR-gate-A0-B1.png2020-09-02 07:27 1.7K 
[IMG]CMOS-AND-gate-A1-B0.png2020-09-02 07:27 1.6K 
[IMG]CMOS-AND-gate-A0-B0.png2020-09-02 07:27 1.6K 
[IMG]CMOS-AND-gate-A1-B1.png2020-09-02 07:27 1.6K 
[IMG]CMOS-OR-gate-A1-B1.png2020-09-02 07:27 1.6K 
[IMG]CMOS-AND-gate-half-A0-B1.png2020-09-02 07:27 1.5K 
[IMG]CMOS-AND-gate-half-A1-B1.png2020-09-02 07:27 1.5K 
[IMG]CMOS-NAND-gate-A0-B1.png2020-09-02 07:27 1.4K 
[IMG]CMOS-NAND-gate-A0-B0.png2020-09-02 07:27 1.4K 
[IMG]CMOS-NAND-gate-A1-B1.png2020-09-02 07:27 1.4K 
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